Job opening for a post-doctoral position at the Institute of Neuroinformatics, University of Zurich and ETH Zurich

We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.

Understanding the computational principles used by the brain and how they are physically embodied is crucial for developing novel computing paradigms and guiding a new generation of technologies that can combine the strengths of industrial-scale electronics with the computational performance of brains.

Complementary metal-oxide-semiconductor (CMOS) transistors are commonly used in very-large-scale-integration (VLSI) digital circuits as a basic binary switch that turns on or off as the transistor gate voltage crosses some threshold. Carver Mead first noted that CMOS transistor circuits operating below this threshold in current mode have strikingly similar sigmoidal current–voltage relationships as do neuronal ion channels and consume little power; hence they are ideal analogs of...

A simple learning rule that implements a spatial map can be used for online correction of position estimates in a neuromorphic head direction cell system.