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VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality »

Stefan Scholze, Stefan Schiefer, Johannes Partzsch, Stephan Hartmann, Christian Georg Mayr, Sebastian Höppner, Holger Eisenreich, Stephan Henker, Bernhard Vogginger, and Rene Schüffny

We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.

Connecting in 3D »

Sunny Bains

I'm currently reading Ray Kurzweil's book, The Singularity is Near, which I'll properly review later. Among other things, the book talks about the supposed imminence of our being able to simulate the brain. I'm afraid I'm not convinced by his...
Address-event-representation tools »

Alejandro Linares-Barranco and Antón Civit-Balcells

European-funded boards will support eight million events per second.
Word-serial address-event representation workshop »

Kwabena Boahen and Timothy K. Horiuchi

Researchers are trained in a new protocol that allows communication between multiple neurons on multiple chips.
Interfacing with address events »

Vittorio Dante, Paolo Del Giudice, and Adrian M. Whatley

A general-purpose board allows data acquisition from, and simulation of, complex neuromorphic systems.


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